FM 2015 Main Track: Accepted Papers
Semantics-Preserving Simplification of Real-World Firewall Rule Sets
A Fully Verified Container Library
Rigorous Estimation of Floating-Point Round-off Errors with Symbolic Taylor Expansions
Using Real-Time Maude to Model Check Energy Consumption Behavior
Verifying Parameterized Timed Security Protocols
Abstraction of Elementary Hybrid Systems by Variable Transformation
Parameter Synthesis through Temporal Logic Specifications
Typed First-Order Logic
A Specification Language for Static and Runtime Verification of Data and Control Properties
Automated Circular Assume-Guarantee Reasoning
Static Optimal Scheduling for Synchronous Data Flow Graphs with Model Checking
Static Differential Program Analysis for Software-Defined Networks
Automated Verification of RPC Stub Code
QPMC: A Model Checker for Quantum Programs and Protocols
Privacy by design in practice: reasoning about privacy properties of biometric system architectures
Towards Formal Verification of Orchestration Computations Using the K Framework
Probabilistic Bisimulation for Realistic Schedulers
Verifying the Safety of a Flight-Critical System
Narrowing operators on template abstract domains
Trace-Length Independent Runtime Monitoring of Quantitative Policies in LTL
Model-Based Problem Solving for University Timetable Validation and Improvement
Safety, Liveness and Run-time Refinement for Modular Process-Aware Information Systems with Dynamic Sub Processes
Property-Driven Fence Insertion using Reorder Bounded Model Checking
Counterexamples for Expected Rewards
Proving Safety with Trace Automata and Bounded Model Checking
A framework for correctness criteria on weak memory models
Verifying Opacity of a Transactional Mutex Lock
The Semantics of Cardinality-based Feature Models via Formal Languages
Certificates for Parameterized Model Checking
Detection of Design Flaws in the Android Permission Protocol through Bounded Verification
Direct formal verification of liveness properties in continuous and hybrid dynamical systems
Certified Reasoning with Infinity
FM 2015 Industry Track: Accepted Papers
Using Simulink Design Verifier for automatic generation of requirements-based testing
Case Study: Static Security Analysis of the Android Goldfish Kernel
Analyzing the Restart Behavior of Industrial Control Applications
Eliminating static analysis false positives using loop abstraction and bounded model checking
Formalizing the Concept Phase of Product Development at Philips Healthcare
Software Development and Authentication for Arms Control Information Barriers
Autofunk: an inference-based formal model generation framework for production systems.
Practices for Formal Models as Documents: Evolution of VDM Application to Mobile FeliCa IC Chip Firmware
Formal Virtual Modelling and Data Verification for Supervision Systems
FM 2015 Doctoral Symposium: Accepted Papers
Specification and verification of real-time systems
Component-based CPS Verification: A Recipe for Reusability
Inheritance and refinement of trustworthy component-based systems
Test-Case Generation via Language Inclusion for Non-Deterministic Networks of Timed Automata
A Code Generator for VDM-RT models
A Formal Model for the Safety-Critical Java Level 2 Paradigm
Privacy-Preserving Social Networks
Properties of Communicating Controllers for Safe Traffic Manoeuvres
A Novel and Faithful Semantics for Feature Modeling
Trace-length Independent Runtime Monitoring